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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
FEATURES
* Fully integrated PLL * 5 LVHSTL outputs each with the ability to drive 50 to ground * Voh (max) = 1.2V * 31.25MHz to 500MHz output frequency range * Spread SmartTM for regenerating spread spectrum clocks * Differential reference clock inputs accept any differential input signal ** Differential reference clock inputs will accept single ended input signal with one of the inputs biased with a resistor network * 31.25MHz to 622MHz input frequency range * LVCMOS / LVTTL control inputs * 3.3V core, 1.8V output operating supply voltage * 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.8mm package lead pitch * 0C to 70C ambient operating temperature * Industrial temperature version available upon request
GENERAL DESCRIPTION
The ICS8725 is a high performance LVHSTL zero delay buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clocks Solutions from ICS. The VCO operates at a frequency range of 250MHz to 500MHz. Utilizing one of the outputs as feedback to the PLL output frequencies up to 500MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.
,&6
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL VDDO VDDA VDDi VEE VEE nQ4 Q4
DIV_SEL0 DIV_SEL1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 DIV_SEL0 DIV_SEL1 REF_CLK1 nREF_CLK1 REF_CLK2 nREF_CLK2 REF_SEL MR 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO
REF_CLK1 nREF_CLK1 REF_CLK2 nREF_CLK2 REF_SEL REF_DIV FB_IN nFB_IN PLL_SEL MR
0 1 /8
0 1 PLL
0 1
/1 /2 /4 /8
ICS8725
21 20 19 18 17
9 10 11 12 13 14 15 16
VDDI nFB_IN FB_IN REF_DIV VEE nQ0 Q0 VDDO
32-Lead LQFP Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8725
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1
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9 10 11 12 13, 28, 29 14, 15 16. 17, 24, 25 18, 19 20, 21 22, 23 26, 27 30 31 32 Name DIV_SEL0 DIV_SEL1 REF_CLK1 nREF_CLK1 REF_CLK2 nRE2_CLK2 REF_SEL MR VDDI nFB_IN FB_IN REF_DIV VEE nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 VDDA PLL_SEL VDDI Input Input Input Input Input Input Input Input Power Input Input Input Power Output Power Output Output Output Output Power Input Power Pullup Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Differential clock select input. When Low selects REF_CLK2 or Pulldown nREF_CLK2. When HIGH selects REF_CLK1 or nREF_CLK1. Resets dividers and determine state of the outputs. Pulldown LVCMOS / LVTTL interface levels. Input and core power supply pin. Connect to 3.3V. Pullup Pulldown Ground pins. Connect to ground. Differential clock outputs. 50 typical output impedance. LVHSTL interface levels. Output power supply pins. Connect to 1.8V. Differential clock outputs. 50 typical output impedance. LVHSTL interface levels. Differential clock outputs. 50 typical output impedance. LVHSTL interface levels. Differential clock outputs. 50 typical output impedance. LVHSTL interface levels. Differential clock outputs. 50 typical output impedance. LVHSTL interface levels. PLL power supply pin. Connect to 3.3V. Selects between the PLL and the reference clock as the input to the dividers. When HIGH select PLL. When LOW selects reference clock. LVCMOS / LVTTL interface levels. Output power supply pin. Connect to 3.3V. Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
8725
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2
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
Test Conditions REF_CLK1, nREF_CLK1, REF_CLK2, nREF_CLK2, FB_IN, nFB_IN DIV_SEL0, DIV_SEL1, REF_SEL, REF_DIV PLL_SEL, MR Minimum Typical Maximum Units
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
TBD
pF
CIN
Input Capacitance
TBD
pF
RPULLUP RPULLDOWN
Input Pullup Resistor Input Pulldown Resistor
51 51
K K
TABLE 3. CONTROL INPUTS FUNCTION TABLE
DIV_SEL1 0 0 1 1 DIV_SEL0 0 1 0 1 FREQUENCY (MHz) MINIMUM 250 125 62.5 31.25 MAXIMUM 250 250 125 62.5
TABLE 4. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Symbol fREF tR tF tDC Parameter Input Reference Frequency Input Rise Time Input Fall Time Input Reference Duty Cycle Measured at 20% to 80% points Measured at 20% to 80% point TBD Test Conditions Minimum 20 Typical Maximum 250 TBD TBD TBD Units MHz ns ns %
8725
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3
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V Inputs -0.5V to VDD+0.5 V Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0C to 70C Storage Temperature -65C to 150C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Symbol VDDI VDDA VDDO IEE Parameter Input Power Supply Voltage Analog Power Supply Voltage Output Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 1.8 Maximum 3.465 3.465 Units V V V mA
TABLE 5B. DIFFERENTIAL DC CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Test Conditions Minimum Typical Maximum Units REF_CLK1, REF_CLK2, VIN = 3.465V 150 A FB_IN IIH Input High Current nREF_CLK1, nREF_CLK2, VIN = 3.465V 5 A nFB_IN REF_CLK1, REF_CLK2, VIN = 0V -5 A IIL Input Low Current FB_IN nREF1, nREF2, nFB_IN VIN = 0V -150 A NOTE: For REF_CLK1, nREF_CLK1 and REF_CLK2, nREF_CLK2 input levels, see VPP and VCMR in AC Characteristics table. Symbol Parameter
TABLE 5C. LVCMOS DC CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Symbol Parameter VIH Input High Voltage DIV_SEL0, DIV_SEL1, REF_SEL, PLL_SEL, REF_DIV, MR DIV_SEL0, DIV_SEL1, REF_SEL, PLL_SEL, REF_DIV, MR DIV_SEL0, DIV_ SEL1, REF_DIV, REF_SEL, MR PLL_SEL IIL Input Low Current DIV_SEL0, DIV_ SEL1, REF_DIV, REF_SEL, MR PLL_SEL
8725
Test Conditions
Minimum 2
Typical
Maximum 3.765
Units V
VIL
Input Low Voltage
-0.3 VIN = 3.465V VIN = 3.465V VIN = 0V VIN = 0V -5 -150
0.8 150 5
V A A A A
IIH
Input High Current
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4
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
Test Conditions Minimum 1.0 Typical Maximum 1.2 Units V V V
TABLE 5D. LVHSTL DC CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
0 0.4 40% x (VOH-VOL) 60% x (VOH-VOL) VOX Output Crossover Voltage + VOL + VOL NOTE 1: Outputs terminated with 50 to ground. The power dissipation of a terminated output pair is 32mW.
TABLE 6. AC CHARACTERISTICS, VDDI=VDDA=3.3V5%, VDDO=1.8V5%, TA=0C TO 70C
Symbol Parameter fMAX VPP VCMR tpLH tpHL Maximum Output Frequency Peak-to-Peak Input Voltage Common Mode Input Voltage Propagation Delay, Low-to-High Propagation Delay, High-to-Low REF_CLK1, PLL Reference nREF_CLK1 Zero Delay; REF_CLK2, NOTE 2 nREF_CLK2 Output Skew; NOTE 3 Cycle-to-Cycle Jitter PLL Lock Time Output Rise Time Output Fall Time Output Pulse Width Output Enable Time Output Disable Time 0MHz f 500MHz f = 500MHz tEN tDIS TBD TBD tCYCLE/2 -TBD TBD tCYCLE/2 2.08 f = 500MHz f = 500MHz PLL_SEL=0V, 0MHz f 500MHz PLL_SEL=0V, 0MHz f 500MHz PLL_SEL=3.3V, fREF=TBD, fVCO=TBD Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 TBD TBD TBD TBD ns ns Test Conditions Minimum Typical Maximum 500 Units MHz
t(O)
-100
TBD
100
ps
tsk(o) tjit(cc) tL tR tF tPW
100 100 TBD TBD TBD tCYCLE/2 +TBD TBD TBD TBD
ps ps
ps ps ns ns ns ns
NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50 to VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent pairs of cycles.
8725
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5
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
D
D2
1 2 3
32
25 24
L
E
E1
E2
N
8 9
17 16
e
A
A2
D1 -CSEATING PLANE
ccc C
A1
b
c
TABLE 7. PACKAGE DIMENISIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.60 0.75 7 0.10 1.40 0.37 MINIMUM NOMINAL 32 1.60 0.15 1.45 0.45 0.20 MAXIMUM
q
ccc
Reference Document: JEDEC Publication 95, MS-026
8725
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6
REV. A MARCH 5, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8725
1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
Marking ICS87251 ICS8725 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 2000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8725Y ICS8725YT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8725
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7
REV. A MARCH 5, 2001

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